1. Field of the Invention
The present invention relates to the field of display, and in particular to a gate driver on array (GOA) circuit for thin film transistor (TFT) based on low temperature poly-silicon (LTPS) semiconductor.
2. The Related Arts
As the liquid crystal display (LCD) shows the advantages of being thin, low power-consumption, and no radiation, the LCD is widely used in various devices, such as, liquid crystal TV, mobile phones, PDA, digital camera, PC monitors or notebook PC screens as well as the leading technology in tablet PCs.
The gate driver on array (GOA) technology is the array substrate column drive technology, by using the array substrate process for the LCD panel to manufacture the driver circuit for the horizontal scan line in the area around the active area on the substrate to replace the external integrated circuit (IC) to perform driving the horizontal scan lines. GOA technology can reduce the bonding process for the external IC and reduce cost, as well as the ability to realize narrow-border or borderless panels, and is used by many types of displays.
As the low temperature poly-silicon (LTPS) semiconductor TFT develops, the LTPS-TFT LCD gains much attention. The LTPS-TFT LCD has the advantages of high resolution, fast response, high luminance, and high opening ratio. Because the LTPS has a more orderly arrangement than the a-Si, the LTPS has ultra-high electron migration rate, 100 times higher than the a-Si. The LTPS can use GOA technology to manufacture the gate driver circuit on the TFT substrate to achieve system integration, save space and the cost for driver IC.
Refer to FIG. 1. The known GOA circuit for LTPS-TFT comprises: a plurality of cascade GOA units, for a positive integer n, the n-th stage GOA unit comprising: a first TFT T1, with a gate connected to an M-th clock signal CK(M), a source connected to an output end G(n−1) of an (n−1)-th stage GOA unit, and a drain connected to a third node K(n); a second TFT T2, with a gate connected to a first node Q(n), a source connected to an (M+1)-th clock signal CK(M+1), and a drain connected to an output end G(n); a third TFT T3, with a gate connected to an (M+2)-th clock signal CK(M+2), a drain connected to the third node K(n), and a source to an output end G(n+1) of an (n+1)-th stage GOA unit; a fourth TFT T4, with a gate connected to an (M+3)-th clock signal CK(M+3), a drain connected to the output end G(n), and a source connected to a constant low voltage VGL; a fifth TFT T5, with a gate connected to a constant high voltage VGH, a source connected to the third node K(n), and a drain connected to first node Q(n); a sixth TFT T6, with a gate connected to a second node P(n), a drain connected to the third node K(n), and a source connected to a constant low voltage VGL; a seventh TFT T7, with a gate connected to the second node P(n), a drain connected to the output end G(n), and a source connected to a constant low voltage VGL; an eighth TFT T8, with a gate connected to the third node K(n), a drain connected to the second node P(n), and a source connected to a constant low voltage VGL; a ninth TFT T9, with a gate and a source connected to the (M+1)-th clock signal CK(M+1), and a drain connected to the second node P(n); a first capacitor C1, with one end connected to the first node Q(n) and the other end connected to the output end G(n); and a second capacitor C2, with one end connected to the second node P(n) and the other end connected to the constant low voltage VGL.
The GOA circuit in FIG. 1 can scan forward or backward, and the forward scan process and the backward scan process are similar. Refer to FIG. 1 and FIG. 2. During forward scanning, scan process is as follows: first, both the M-th clock signal CK(M) and the output end G(n−1) of the (n−1)-th GOA unit provide a high voltage, the first TFT T1 and the fifth TFT T5 are turned on, and the first node Q(n) is pre-charged to high voltage; then, both the M-th clock signal CK(M) and the output end G(n−1) of the (n−1)-th GOA unit become low, the (M+1)-th clock signal CK(M+1) provides a high voltage, the first node Q(n) stays high due to the storage effect of the first capacitor C1, the second TFT T2 is turned on, the output end G(n) outputs the high voltage of the (M+1)-th clock signal CK(M) so that the first node Q(n) is raised to an even higher voltage, at the same time, the eighth TFT T8 is turned on, the second node P(n) is pulled down to the constant low voltage VGL, the sixth TFT T6 and the seventh TFT T7 are turned off; then, the (M+2)-th clock signal CK(M+2) and the output end G(n+1) of the (n+1)-th GOA unit provide high voltage, the first node Q(n) stays high, the (M+1)-th clock signal CK(M+1) becomes low, the output end G(n) outputs the low voltage of the (M+1)-th clock signal CK(M+1); and then, the M-th clock signal CK(M) provides high voltage again, the output end G(n−1) of the (n−1)-th GOA unit stays low, the first TFT T1 is turned on to pull down the first node Q(n) to low voltage, the eighth TFT T8 is turned off; then, the (M+1)-th clock signal CK(M+1) provides high voltage, the ninth TFT T9 is turned on, the second node P(n) is charged to high voltage, the sixth TFT T6 and the seventh TFT T7 are turned on to continue pulling down the first node Q(n) and output end G(n) to the constant low voltage VGL, respectively, the second node P(n) stays high under the storage effect of the second capacitor C2, the sixth TFT T6 and the seventh TFT T7 stay turned on during the duration of a frame to keep the first node Q(n) and the output end G(n) at low voltage.
In the above GOA circuit for LPTS-TFT, because the sixth TFT T6 and the seventh TFT T7 operate for a long duration, a threshold voltage shift (Vth shift) may occur to the sixth TFT T6 and the seventh TFT T7, which lowers the circuit stability and may lead to abnormal output for GOA circuit.